Programmed logic arrays (PLAs) are used in the control units of microprocessors in data processing systems. A microprocessor can be viewed as the brains of a data processing system or computer. A PLA is a crosspoint array of transistors arranged to perform logic computations or transformations--that is, to process data by delivering data signal outputs as determined by data signal inputs in accordance with prescribed logic transformation rules, such rules typically involving AND, OR, and NOR logic operations to be performed upon the data inputs. In turn, the transformation rules are determined by the configuration of the array of transistors in the PLA, as more fully described below.
A PLA typically comprises two main portions known as the AND plane and the OR plane, respectively. Outputs of the AND plane are inputs to the OR plane. Each plane is in the form of a crosspoint logic array, i.e., a rectangular array of parallel row lines and parallel column lines intersecting at crosspoints. At each of selected crosspoints is located and connected a crosspoint driver transistor, the selection of such crosspoints depending upon and in accordance with the desired logic transformation rule to be implemented by the plane. Basically, each plane operates in a similar way in order to perform the NOR logic function transformation upon binary digital data (1's and 0's, corresponding to high and low voltage levels, respectively) entering the plane.
The specifics of the NOR functions implemented by the AND and OR planes are determined by the configurations in the respective planes of the selected crosspoints, i.e., the configurations formed by presences vs. absences of driver transistors connected at the various crosspoints. More specifically, input data to a given plane is applied along parallel (either row or column) input lines (wires) to the gate electrodes of the crosspoint driver transistors in the logic array of that plane, and output data from the plane emanates along parallel (column or row) output lines orthogonal to the input lines. Each such output line is connected to a ground node via the mutually parallel source-drain (high current-carrying) paths of all driver transistors located at crosspoints on that output line.
Each output line of the AND plane is also called a "wordline" and serves as an input line of the OR plane. Typically the crosspoint driver transistors are all MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). Each MOSFET has a pair of controlled source and drain or high-current-carrying terminals as well as a gate electrode control or low-current-carrying terminal.
A useful mode of operation of an AND plane (and similarly of an OR plane) involves clocked PMOS (p-channel MOS) load or pull-up transistors--in order to precharge to a high voltage level (essentially V.sub.DD) each of the output lines of the AND plane during each precharge phase--in combination with NMOS (n-channel MOS) crosspoint driver transistors, and a clocked ground switch or pull-down transistor--in order to discharge the output lines to a low voltage level (essentially V.sub.SS) during each evaluation or logic computation phase. Each clock cycle commences with a precharge phase of the AND plane. This precharge phase is typically immediately followed by a precharge phase of the OR plane--during which the AND plane evaluates the logic for that cycle. Thus, the precharge phase of the OR plane is the evaluation phase of the AND plane.
During each precharge phase of a given plane, all pull-up transistors in that plane are on while the pull-down transistor is off, in order to ensure precharging of all output lines of that plane to the high level regardless of the on vs. off conditions of the various (crosspoint) driver transistors. At the end of the precharge phase, or a very short time thereafter, the logic evaluation (or computation) phase begins. During the evaluation phase, the pull-up transistors are all off and the pull-down transistor is on. Thereby each output line either is pulled down to a low (or ground) level or remains at the high level, depending upon whether or not at least one driver on that output line is on. In any event, if at least one driver on a particular output line is on during evaluation, then that output line discharges via the driver and the pull-down transistor to ground.
A PLA that operates in the above-described manner has been disclosed, for example, by E. Hebenstreit et al in a paper entitled "High-Speed Programmable Logic Arrays in ESFI SOS Technology," published in IEEE Journal of Solid State Circuits, Vol. SC-11, pp. 370-374 (1976) at p. 371 (FIG. 3 therein).
The speed of operation of a PLA depends upon, among other things, the time it takes to ensure that the output lines of the AND plane and of the OR plane are properly precharged to the high level during the corresponding precharge phase: the longer the required precharge phase, the lower the speed of operation.
Since the slowest operating portion of a microprocessor is ordinarily the PLA, and since the lengths (durations) of all phases of each clock cycle are ordinarily made the same, it is important for high operating speed that the required time or phase duration for each phase be kept as small as feasible. Of all phases in a PLA, the precharge phase tends to be the longest. Therefore, it would be desirable to find a way to reduce the required duration of the precharge phase of the plane in a PLA.